In wafer fabrication technology, two tests are typically performed to determine intrinsic flash cell performance for flash technology qualification. As a first part, a single cell endurance threshold voltage, Vt window closure test is performed, hereinafter referred to as Endu test, and secondly a charged pump characterization test is performed, hereinafter referred to as CP test. As part of the Endu test, up to two million program/erase cycles are performed on a flash cell. After the two million cycles, Vtp (Vt after programming) and Vte (Vt after erase) are measured, and Vtp (2 mil)−Vte (2 mil) is calculated. For the CP test, a flash cell is subjected to one million program/erase cycles. After the one millionth cycle, Icp, pk (peak charge pump current) is measured, and the charge trapped after program (Ctp) is calculated from the measured Icp, pk.
The above described intrinsic flash cell performance test has a number of problems, including a significant time investment to perform the relevant program/erase cycles. For example, it typically takes two weeks to run two million program/erase cycles for the Endu test and it may typically take 1.5 weeks to run the one million program/erase cycles for the CP test. This results in a total lead time of about 3.5 weeks. Furthermore, for the Endu test, defects induced breakdown may be encountered, and typically occurs between 50,000 to 300,000 cycles. If defects induced breakdown occurs, then the test needs to restart, causing further substantial delay.
A need therefore exists to provide a method and system that seeks to address at least one of the above problems.